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Design of Analog CMOS Integrated Circuits; Mc-Graw Hill Inc.: New York, NY, USA, 2015. [Google Scholar]Hesham, O. Fast and accurate technique for comparator offset voltage simulation. Microelectron. J. 2019, 89, 91–97. [Google Scholar]Peng, X.; Gao, A.; Chen, Z.; Zhang, H.; Li, Y.; Cao, W.; Liu, X.; Tang, H. A Novel Comparator Offset Calibration Technique for SAR ADCs. In Proceedings of the 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Shenzhen, China, 6–8 June 2018. [Google Scholar]Zhang, Y.; Cai, J.; Li, X.; Zhang, Y.; Su, B. A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration. Microelectron. J. 2021, 116, 105–244. [Google Scholar] [CrossRef] Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 2. The common-mode buffer. Figure 2. The common-mode buffer. Figure 3. The symmetrical OTA. Figure 3. The symmetrical OTA. Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 6. Differential preamplifier with offset voltage. Figure 6. Differential preamplifier with offset voltage. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 8. Control logic circuit. Figure 8. Control logic circuit. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 10. The timing diagram of comparator offset trimming. Figure 10. The timing diagram of comparator offset trimming. Figure 11. The layout of the comparator. Figure 11. The layout of the comparator. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 13. Transient simulation test bench of the proposed comparator. Figure 13. Transient simulation test bench of the proposed comparator. Figure 14. Transient simulation curves of the proposed comparator (ripple = 30 μV). Figure 14. Transient simulation curves of

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Scholar] [CrossRef]Ghasemi, R.; Karami, M.A. A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology. In Proceedings of the 2020 28th Iranian Conference on Electrical Engineering (ICEE), Tabriz, Iran, 4–6 August 2020. [Google Scholar]Qiu, L.; Meng, T.; Yao, B.; Du, Z.; Yuan, X. A High-Speed Low-Noise Comparator with Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2023, 31, 152–156. [Google Scholar] [CrossRef]Bandla, K.; Krishnan, A.H.; Sethi, S.; Pal, D. Design of High Speed and Low Offset SR Latch Based Dynamic Comparator. In Proceedings of the 2020 IEEE Region 10 Symposium (TENSYMP), Dhaka, Bangladesh, 5–7 June 2020. [Google Scholar]Campos, A.L.; Navarro, J.; Luppe, M. Design of a low power 10-bit 12 MS/s asynchronous SAR ADC in 65 nm CMOS. In Proceedings of the 2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI), Sao Paulo, Brazil, 26–30 August 2019; pp. 1–6. [Google Scholar]da Costa, J.P.D.C.; Gounella, R.H.; Bastos, W.B.; Longo, E.; Carmo, J.P. Photovoltaic Sub-Module with Optical Sensor for Angular Measurements of Incident Light. IEEE Sens. J. 2019, 19, 3111–3120. [Google Scholar] [CrossRef]Wang, T.Y.; Li, H.Y.; Ma, Z.Y.; Huang, Y.J.; Peng, S.Y. A Bypass-Switching SAR ADC with a Dynamic Proximity Comparator for Biomedical Applications. IEEE J. Solid-State Circuits 2018, 53, 1743–1754. [Google Scholar] [CrossRef]Enz, C.C.; Temes, G.C. Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization. Proc. IEEE 1996, 84, 1584–1614. [Google Scholar] [CrossRef]Cheng, Y.; Tong, Y. Techniques for offset calibration in comparators. In Proceedings of the 2021 International Conference on Electronic Information Engineering and Computer Science (EIECS), Changchun, China, 23–26 September 2021. [Google Scholar]Kouhalvandi, L.; Aygün, S.; Özdemir, G.G.; Güneş, E.O. 10-bit High-speed CMOS comparator with offset cancellation technique. In Proceedings of the 2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE), Riga, Latvia, 24–25 November 2017. [Google Scholar]Razavi, B.; Wooley, B.A. Design techniques for high-speed, high-resolution comparators. IEEE J. Solid-State Circuits 1992, 27, 1916–1926. [Google Scholar] [CrossRef]Li, J.; Weisheng, X.; Youling, Y. A high-speed and high-resolution CMOS comparator with three-stage preamplifier. J. Semicond. 2010, 31, 045006. [Google Scholar] [CrossRef]Park, H.; Yu, C.; Kim, H.; Roh, Y.; Burm, J. Low Power CMOS Image Sensors Using Two Step Single Slope ADC with Bandwidth-Limited Comparators & Voltage Range Extended Ramp Generator for Battery-Limited Application. IEEE Sens. J. 2020, 20, 2831–2838. [Google Scholar]Li, W.; Li, F.; Liu, J.;

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