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IDEX Biometrics Selects Agnisys IDesignSpec to Aid Development of the Next-Generation ASICs for IoT Security BOSTON — (BUSINESS WIRE) — April 8, 2019 — Agnisys, Inc. today announced that IDEX Biometrics® (OSE: IDEX), the leading provider of fingerprint identification technologies has chosen Agnisys IDesignSpec™ software to aid development of the next-generation ASIC devices for IoT security. With a comprehensive list of patents in the areas of biometrics sensing, design and packaging, IDEX aims to deploy fingerprint sensing technology as the future of IoT security. IDEX Biometrics uses IDesignSpec for designing the register specification from a single specification. IDesignSpec automatically generates the register RTL, UVM models, C Headers, and HTML/PDF documentation needed for the ASIC project. “Using IDesignSpec in our flow has been extremely beneficial. We were able to start from an Excel spreadsheet description of our memory map and use IDesignSpec to create documentation, software header files, verification widgets and RTL code, all of which were changed at the same time,” said Rick Wanzenried, Digital Design Manager, IDEX Biometrics. “This has saved many engineering hours, as we have been able to flawlessly maintain our design and documentation.” “IoT is one of the technological mega trends that will have a great impact to our society in the future,” said Anupam Bakshi, Agnisys CEO and Founder. “We look forward to further enhancing IDesignSpec to meet new requirements as IDEX Biometrics helps to prevent and eliminate theft and fraud in IoT.” About IDesignSpecIDesignSpec is an award-winning product that helps IP/SoC Design architects and engineers to create executable specification for registers and automatically generate output for SW/HW teams. The specifications can be written in Microsoft® Word™ or Excel™, LibreOffice™ with IDesignSpec editor Plugin or text-based industry standard formats like SystemRDL, RALF, IP-XACT. IDesignSpec captures simple as well as special registers, signals, interrupts, and then

Plugin or text based industry standard formats like SystemRDL, RALF, IP-XACT. IDesignSpec generator takes the specifications and builds the synthesizable RTL code, SV-UVM model, C/C++ headers and the documentation in HTML, Word, and PDF formats.The specification captures the hierarchical structure of the designs, and let users define registers, register blocks, references to the register blocks or even references to the other register specification files. Any change required in the functionality can be included in the specs and modified output can be generated. IDesignSpec also offers the assistance to the verification team by generating the verification environment for the registers & memory banks and their interface to the AMBA buses.ARV™ is an add-on product to IDesignSpec that expands an already powerful register specification solution with capability to automate the register specification-creation-verification process for ARM-based SoCs, IP and FPGA semiconductor projects. ARV saves semiconductor teams time and improves quality by enabling complete code coverage for design registers that are the key integration point for semiconductor design, IP, software and interfaces. ARV-Formal uses formal tools such as Mentor Questa® Formal and OneSpin’s DV-Verify 360™ to ensure that Register operations conform to the user specification and ARM standards. ARV-Sim can use Mentor Graphics’ Questa® VIP to create a UVM based simulation environment to verify the registers automatically.About AgnisysAgnisys provides IDesignSpec for specification driven system development for ARM-based designs. Client IP for AMBA buses such as AXI, APB, AHB AXI4LITE, AHB3LITE can be generated using IDesignSpec. Along with synthesizable IP code, a verification test environment,

Properties like “-lowpower” and “power_opt” in tools such as IDesignSpec™ facilitate the integration of these techniques into the design flow, streamlining the implementation of power-optimized solutions.IDesignSpec™, an integral part of the design process, plays a crucial role in generating low-power RTL code. By eliminating redundant assignments and minimizing write operations, IDesignSpec™ ensures that the generated code consumes low power without compromising performance. Leveraging properties like “-lowpower”, “-power_opt”, “clock_enable” IDesignSpec™ incorporates power-saving techniques seamlessly into the design flow, empowering designers to create energy-efficient solutions.As digital devices continue to evolve, the importance of power optimization cannot be overstated. Sustainable and efficient electronic systems rely on the judicious application of power-saving techniques throughout the design process. By incorporating clock gating, low-power switching, and clock enablement strategies, designers can achieve significant power savings without compromising functionality. Moreover, as technology advances and new challenges emerge, continued innovation in power optimization will be essential to meet the demands of an increasingly energy-conscious world.In conclusion, power optimization is not merely a technical consideration but a fundamental imperative for the development of next-generation electronic systems. Through the adoption of innovative techniques and methodologies, designers can pave the way for a more sustainable and energy-efficient future. With tools like IDesignSpec™ facilitating the integration of power-saving techniques, designers are empowered to create cutting-edge solutions that deliver both performance and energy efficiency.

Agnisys Automates Development of ARM-Based Designs With the growing requirement for configurable IP, processor and SoC, the number of registers, access type and interrupts have gone up for the last few years and aggravated the complexity of designs. For example, a design with just 100 addressable registers of 32 bits would add up to 100*2^32 fields and any wrong implementation of data or wrong configuration would cause trouble. Also, registers are widely used in the SoC peripherals like – DMA, UART, PCI, MIPI, Display, Audio, Ethernet etc. It takes a great deal of time and effort for defining registers for the peripherals. To optimize the resource, quality and project delivery schedule, using controllable automation is a prudent choice.Agnisys will showcase its product IDesignSpec™ in ARM® TechCon 10-12 Nov 2015 at Santa Clara, CA. It helps to generate the Registers, FIFOs, Register access, Interrupts, virtual registers, descriptors and Sequences – for ARM-based projects.Agnisys announced the enhanced capability of IDesignSpec for defining registers interfaced with the ARM AMBA® bus interface standard compliance for the configurable IP and SoC design. The latest added features will help ARM designers / architects to create executable specs for the HW/SW interface at an early stage when the business spec is being worked on, and subsequently generate required output for the design & verification phase.The executable specs are easy to write and understand, and give freedom to choose multiple formats. That is, the specifications can be written in MS Word, MS Excel, OpenOffice Cal with IDesignSpec editor

Agnisys to showcase IDesignSpec NextGen at DVCON 2018 Agnisys will showcase IDesignSpec NextGen – the Next Generation product for capturing requirement specification for embedded designs, and automatically generating code from it.IDS NextGen is a multi-platform product which helps user to create SoC specification at an enterprise level. It handles individual IP to sub-system to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV, System RDL. IDS NextGen generates design and verification code for not just registers but sequences in one integrated environment. It reduces the verification time by generating the entire UVM SV and SystemC output sequences.The IDS NextGen product attempts to “understand” the specification using Machine Learning technology and guides the user about issues with the specification. It helps create a standardized specification. Capturing issues in the specification is the extreme form of “Shift-Left” that the industry has been seeing. Agnisys motto is to stop issues from germinating in the first place so that less time is spent on the debug – which is often very costly. Once the specification is entered, user can create custom outputs using a template engine. IDS NextGen now supports all current prevailing input and output formats.The NextGen product also supports special safety and reliability requirements for Automotive and IoT sectors. Agnisys would be exhibiting IDS NexGen at DVCON 2018.Exhibit Information:Booth 805 | February 26 – March 1, 2018 | DoubleTree Hotel, San Jose, CA