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0x408000000xC08000000x834000000xC85800000Answer (Detailed Solution Below) Option 2 : 0xC0800000 Concept: In IEEE- 754 single precision format, a floating-point number is represented in 32 bits. Sign bit (MSB) Biased Exponent (E’) (8 bits) Normalized Mantissa (M’) (23 bits) Sign bit value 0 means positive number, and 1 means a negative number.The floating-point number can be obtained by formula: ± 1. M × 2(E-127)Data:Content of R1: 0x 42200000 (0x means Hexadecimal notation)Content of R2: 0x C1200000Calculation:Content of R1 in Hex (0x) is 42200000. After converting into binary, it can be represented in IEEE- 754 format as: 0 100 0010 0 010 0000 0000 0000 0000 0000 Sign bit is 0 i.e. the number is positiveBiased Exponent (E’) = 100 0010 0 = 132Normalized Mantissa (M) = 010 0000 0000 0000 0000 0000 = .25Therefore, the number in register R1 = + 1.25 * 2(132-127) = 1.25 × 32 = 40Content of R2 in Hex (0x) is C1200000. After converting into binary, it can be represented in IEEE- 754 format as: 1 100 0001 0 010 0000 0000 0000 0000 0000 Sign bit is 1 i.e. the number is negativeBiased Exponent (E’) = 100 0001 0 = 130Normalized Mantissa (M) = 010 0000 0000 0000 0000 0000 = .25Therefore, the number in register R1 = - 1.25 * 2(130-127) = -1.25 * 8 = -10R3 = R1/R2 = 40/-10 = -4Since the number is negative, Sign bit (MSB) = 1Converting 4 into binary of a floating point gives: (100.0)2Representing it into normalized form gives: (1.000000….) × 22Therefore, Mantissa is 23 bits of all 0sBiased Exponent (E’) = E+ 127 = 2+127 = 129 = (10000001)2It can be represented in IEEE- 754 format as: 1 100 0000 1 000 0000 0000 0000 0000 0000 Converting it into Hex format gives: 0x C0800000 The decimal floating-point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is _____ 0xC22060000xC20066660xC20060000xC2206666Answer (Detailed Solution Below) Option 4 : 0xC2206666 Concept:32-bit floating-point representation of a binary number in IEEE- 754 is Sign (1 bit) Exponent (8 bit) Mantissa bit (23 bits) In IEEE-754 format, 32-bit (single precision)(-1)s × 1.M × 2E – 127Calculation:Convert: 40.1 to binaryStep 1: convert 40 2 40 2 20 0 2 10 0 2 5 0 2 2 1 2 1 0 0 1 ↑ (40)10 = (101000)2Step 2: convert .1 to binary0.1 × 2 = 0.2 (0)0.2 × 2 = 0.4 (0)0.4 × 0.2 = 0.8 (0)0.8 × 0.2 = 1.6 (1)0.6 × 0.2 = 1.2 (1)0.2 × 0.2 = 0.4 (0) and so onGiven binary number is(40.1)10 = (101000.000110011001100…)2(40.1)10 = 1.0100 0000 1100 1100 … × 25Signed (1 bit) = 1 (given number is negative)Exponent (8 bit) = 5 + 127 = × 10-1 Concept:32-bit floating-point representation of a binary number in IEEE- 754 is Sign (1 bit) Exponent (8 bit) Mantissa bit (23 bits) Calculation:Given binary number is00111110011011010000000000000000Here, sign bit is 0. So, number is positive. 0 01111100 11011010000000000000000 Exponent bits = E = 01111100 = 124 (in decimal)Mantissa bits M = 11011010000000000000000In IEEE-754 format, 32-bit (single precision) (-1)s × 1.M × 2E – 127 = (-1)0 × 1.1101101 × 2124 – 127= 1.1101101 × 2-3= (1 + 2-1 + 2-2 + 2-4 + 2-5 + 2-7) × 2-3= 0.231 = 2.31 × 10-1 ≈ 2.27 × 10-1 In IEEE floating point representation, the hexadecimal number 0xC0000000 corresponds to –3.0–1.0–4.0–2.0Answer (Detailed Solution Below) Option 4 : –2.0 Concept:32-bit floating-point representation of a binary number in IEEE- 754 is Sign (1 bit) Exponent (8 bit) Mantissa bit (23 bits) Calculation:Binary number is0xC0000000 = (11000000000000000000000000000000)2Here, the sign bit is 1. So, the number is negative. 1 10000000 00000000000000000000000 Exponent bits = E = 10000000 = 128 (in decimal)Mantissa bits M = 00000000000000000000000In IEEE-754 format, 32-bit (single precision)(-1)s × 1.M × 2E – 127= (-1)1 × 1. 0 × 2128 – 127= -1 × 1.0 × 2= -2In IEEE floating-point representation, the hexadecimal number 0xC0000000 corresponds to -2. Let R1 and R2 be two 4-bit registers that store numbers in 2’s complement form. For the operation R1 + R2, which one of the following values of R1 and R2 gives an arithmetic overflow? R1 = 1011 and R2 = 1110R1 = 1100 and R2 = 1010R1 = 0011 and R2 = 0100R1 = 1001 and R2 = 1111Answer (Detailed Solution Below) Option 2 : R1 = 1100 and R2 = 1010 The correct answer is option 2.Concept:Stored numbers in registers R1 and R2 are in 2's complement form. Register size is 4 bits. The range of numbers in 2's complement form is -8 to +7. If R1 + R2, the result is out of the above range, then it is overflow.The given data,Given two four-bit registers R1 and R2.Option 1: R1 = 1011 and R2 = 1110False, R1 = 1 0 1 1 = -(0101)= -5+ R2 = 1 1 1 0 = -(0010)= -2----------------------------------------------- 1 0 0 1 = = -7 Here No overflow occurred, because sign bit is same for (R1 + R2 ).Option 2: R1 = 1100 and R2 = 1010True,R1 = 1 1 0 0 = -(0100)= -4+ R2 = 1 0 1 0 = -(0110)= -6 -------------------------------------------- 0 1 1 0 = = -10 Here Overflow occurred because the sign bit is different for (R1 + R2 ).Option 3: R1 = 0011 and R2 = 0100False,R1 = 0 0 1 1 = +(0011)= +3+ R2 = 0 1 0

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